Design of FFNN architecture for power quality analysis and its complexity challenges on FPGA

As we all know, power quality (PQ) issues are a major concern these days. Field programmable gate array (FPGA) essential in PQ analysis, particularly smart meters for data processing, storage, and transmission. One of the most significant advantages FPGA is its reconfigurability, with vast hardware resources that can be used to implement complex as well time-critical processing units. Because architecture supports fixed point arithmetic, loss occurs path unit, necessitating realization event detection module, classification model more accurate than software implementation algorithms. The majority work reported, feed forward neural network (FFNN) structure occupying large number multipliers adders classification, reported has not addressed minimize FFNN instead have improving accuracy. Based on issues, this paper addresses challenges design by proposing improved fast architectures. proposed using optimum resources. based classifier designed perform 99.5% processor operates at maximum frequency 238 MHz.